Implementation and Virtual Prototyping of a 2.6 GHz ARM® Cortex®-A15 in a big.LITTLE SoC
Fujitsu recently taped out a complex visual computing SoC with a dual-core Cortex-A15 / dual-core Cortex-A7 MPCore big.LITTLE processing subsystem and ARM Mali T624 CPU. This session will highlight enabling technologies in Design Compiler and IC Compiler which, together with the Synopsys high performance core (HPC) methodology, delivered an impressive 2.6 GHz frequency on the Cortex-A15 processor sub-system. These technologies include improved predictability by using Synopsys physical guidance (SPG) and layer-aware optimization, clock mesh to reduce on-chip variation and skew and Final-stage Leakage Recovery to minimize leakage power. The session will also provide an overview of Fujitsu’s use of the Synopsys Virtualizer™ Development Kit (VDK) for the big.LITTLE configuration, used to accelerate software development.